1. Field of the Invention
The present invention relates to a thin film transistor and a manufacturing method of the same, and more particularly, to a thin film transistor with sub-gates and Schottky source/drain and a manufacturing method of the same.
2. Description of the Prior Art
FIG. 1 shows the structural diagram of a conventional thin film transistor. In FIG. 1, 10 represents a glass or quartz substrate; 12 denotes a semiconductor layer, eg. polysilicon; 14 represents a doping area on the semiconductor 12, which serves as source/drain of the thin film transistor 1; and 16 represents gate oxide layer; and 18 represents gate.
The shortcomings of the conventional thin film transistor 1 are:
Because implant doping and the following annealing must be carried out, it is not advantageous to lower the process temperature.
Depending on the type of dopant in the source/drain, the operation mode of a thin film transistor is restricted as n type or p type, which does not allow for bi-channel operation.
Please refer to the curve a in FIG. 2., which illustrates the characteristic of drain current (ID) vs gate voltage (VG) of a conventional thin film NMOS transistor. From FIG. 2, it is observed that when the gate voltage is negative, there is still drain current leakage generated. This is caused by the off-stage leakage resulted from the strong field induced between the drain and gate when negative gate voltage is applied and grain boundary traps in the semiconductor 12.
The object of the present invention is to provide a novel manufacturing method for a thin film transistor with sub-gates and Schottky source/drain, which omits the steps of distribution doping in source/drain, and follow-up annealing to lower complexity and production costs. This is beneficial to lower the process temperature.
Another object of the present invention is to provide a novel thin film transistor with a sub-gate and Schottky source/drain, which allows for a transistor element to operate in both n type and p type channels by simply adjusting the biased-voltage of the sub-gate.
Another object of the present invention is to apply voltage to the sub-gate to induce the formation of an electrical junction, which takes place the conventional source/drain extension; which results in the reduction of cut-off leakage.
To achieve the above-mentioned objects, the invention discloses a first manufacturing method for forming a thin film transistor with sub-gates and Schottky source/drain, comprising the steps of:
(a)providing an insulation substrate; (b)forming two island-shaped sub-gate layers on the insulation substrate; (c)forming a first insulation layer on the island-shaped sub-gate layers and the insulation substrate; (d)forming a second insulation layer on the first insulation layer; (e)planarizing the second insulation layer to expose the first insulation layer; (f)forming an island-shaped semiconductor layer on the first and second insulation layers; (g)forming a gate dielectric layer on the surface of the island-shaped semiconductor layer; (h)forming an island-shaped main gate layer on the gate dielectric layer; (I)forming insulation spacers on the side walls of the island-shaped main gate layer and exposing the island-shaped semiconductor layer on two sides of the insulation side walls; (j)forming a metal-containing replacement layer on the island-shaped semiconductor layer of two sides of the insulation side walls; wherein the replacement layer and the island-shaped semiconductor layer existing underneath the insulation spacers form a Schottky contact, which serves as the Schottky source/drain in the thin film transistor.
To achieve the above-mentioned objects, the invention discloses a second manufacturing method for forming a thin film transistor with sub-gates and a Schottky source/drain, comprising the steps-of:
(a)providing an insulation substrate; (b)forming two island-shaped sub-gate layers on top of the insulation substrate;(c)forming a first insulation layer on the island-shaped sub-gate layer and the insulation substrate; (d)forming a second insulation layer on the first insulation layer; (e)planarizing the second insulation layer to expose the first insulation layer; (f)forming an island-shaped semiconductor layer on the first and second insulation layers; (g)forming a gate dielectric layer on the surface of the island-shaped semiconductor layer; (h)forming an island-shaped main gate layer on the gate dielectric layer; (I)forming an island-shaped mask layer to cover the island-shaped main gate layer and the gate dielectric layer located at two sides of the island-shaped main gate layer; (j)removing the gate dielectric layer on two sides of the island-shaped mask layer to expose the island-shaped semiconductor layer; (k)forming a metal-containing replacement layer on the exposed island-shaped semiconductor layer on two sides of the island-shaped mask layer; wherein the replacement layer and the island-shaped semiconductor layer existing underneath the island-shaped mask layer form a Schottky contact, which serves as the Schottky source/drain in the thin film transistor; (1) removing the island-shaped mask layer.
To achieve the above-mentioned objects, the invention discloses a third manufacturing method for forming a thin film transistor with sub-gates and Schottky source/drain, comprising the steps of:
(a)providing an insulation substrate; (b)forming an island-shaped semiconductor layer on top of the insulation substrate; (c)forming a first insulation layer, a first conductive layer and a second insulation layer on the island-shaped semiconductor layer and the insulation substrate sequentially; (d)defining and etching the second insulation layer and the first conductive layer to form two sub-gate stack layers on the first insulation layer and the island-shaped semiconductor layer; (e)forming insulation spacers on the side walls of the two sub-gate stack layers; (f)removing the first insulation layer to expose the island-shaped semiconductor layer; (g)forming a gate dielectric layer on the island-shaped semiconductor layer; (h)defining and forming a main gate layer on the gate dielectric layer between the two sub-gate stack layers; (i)removing the gate dielectric layer which is not covered by the main gate layer and the two sub-gate stack layers to expose the island-shaped semiconductor layer; (j)forming a metal-containing replacement layer on the exposed island-shaped semiconductor layer; wherein the replacement layer and the island-shaped semiconductor layer existing underneath the island-shaped insulation spacers form a Schottky contact, which serves as the Schottky source/drain in the thin film transistor.
To achieve the above-mentioned objects, the invention discloses a fourth manufacturing method for forming a thin film transistor with sub-gates and Schottky source/drain, comprising the steps of:
(a)providing an insulation substrate; (b)forming two island-shaped semiconductor layers on the insulation substrate; (c)forming a gate dielectric layer on the surface of the island-shaped semiconductor layer; (d)forming an island-shaped main gate layer on the gate dielectric layer; (e)forming insulation spacers on the side walls of the island-shaped main gate layer; (f)removing the gate dielectric layer on the two sides of the insulation spacers to expose the island-shaped semiconductor layer; (g)forming a metal-containing replacement layer on the exposed island-shaped semiconductor layer; wherein the replacement layer and the island-shaped semiconductor layer existing underneath the insulation side walls form a Schottky contact, which serves as the Schottky source/drain in the thin film transistor; (h)removing the metal layer which has not reacted to form the replacement layer; (I) forming an insulation layer to cover the main gate layer, insulation spacer, and the Schottky source/drain; (j) planarizing the insulation layer; and (k)forming an island-shaped sub-gate layer on the top of the main gate layer, the two ends of the island-shaped sub-gate layer overlap with the Schottky source/drain respectively.
To achieve the above-mentioned objects, the invention discloses a fifth manufacturing method for forming a thin film transistor with sub-gates and Schottky source/drain, comprising the steps of:
(a)providing an insulation substrate; (b)forming an island-shaped semiconductor layer on top of the insulation substrate; (c)forming a gate dielectric layer on the surface of the island-shaped semiconductor layer; (d)forming an island-shaped main gate layer on top of the gate dielectric layer; (e)forming an insulation layer to cover the island-shaped main gate layer and the gate dielectric layer; (f)defining and etching the insulation layer and gate dielectric layer, and forming an insulation mask layer to cover a first portion of the island-shaped main gate layer and the gate dielectric layer, and an insulation spacer on the side wall of second portion of the island-shaped main gate layer and the gate dielectric layer; thus the portions of island-shaped semiconductor layer not covered by the main gate, insulation mask layer, and spacer are exposed; (g)forming a metal-containing replacement layer on the insulation spacer and the exposed island-shaped semiconductor layer; wherein the replacement layer and the island-shaped semiconductor layer underneath the insulation spacer and the insulation mask layer form the Schottky contact and serve as the Schottky source and drain, respectively of the thin film transistor; (h)removing the metal layer which has not reacted in the formation of the replacement layer; (I)forming a second insulation layer covering the main gate layer, insulation spacer, insulation mask layer and the Schottky source/drain; (j)planarizing the second insulation layer; and (k)forming an island-shaped sub-gate layer over the main gate layer, and two end portions of the island-shaped sub-gate layer overlap with the Schottky source/drain respectively.
The first structure of the thin film transistor with sub-gates and Schottky source/drain of the invention is comprised of: (1) two sub-gate structures, forming on an insulation substrate; wherein each sub-gate structure is comprised of: a sub-gate layer; and a sub-gate dielectric layer forming on the sub-gate layer; (2) a semiconductor thin film layer forming on the two sub-gate structures, and serve as the channel region of the thin film transistor; (3)two metal-containing Schottky source/drain regions formed on two sides of the channel region and forming Schottky contacts with the channel region respectively; (4)a main gate dielectric layer formed on the channel region; wherein the thickness of the main gate dielectric layer is less than the thickness of the sub-gate dielectric layer; (5)a main gate layer formed on the central area of the main gate dielectric layer to expose the main gate dielectric layer on two sides of the main gate layer; where the main gate layer and the main gate dielectric layer underneath it form a main gate structure.
The second structure of the thin film transistor with sub-gates and Schottky source/drain of the invention is comprised of: (1) a semiconductor thin film layer formed on an insulation substrate to serve as the channel region of the thin film transistor; (2)two metal-containing Schottky source/drain regions formed on two sides of the insulation, substrate and the channel region and forming Schottky contacts with the channel region, respectively; (3)two sub-gate structures formed on the channel region;; wherein each sub-gate structure is comprised of: a sub-gate dielectric layer; and a sub-gate layer formed on top of the sub-gate dielectric layer; (4)a main gate dielectric layer formed on the channel region between the two sub-gate structures; wherein the thickness of the main gate dielectric layer is less than that of the sub-gate dielectric layer; (5)a main gate layer formed on top of the main gate dielectric layer; wherein the main gate layer and the sub-gate layer are isolated from each other.
The third structure of the thin film transistor with sub-gates and Schottky source/drain of the invention is comprised of: (1) a semiconductor thin film layer formed on an insulation substrate to serve as the channel region of the thin film transistor; (2)two metal-containing Schottky source/drain regions formed on two sides of the insulation substrate and the channel region and form Schottky contacts with the channel region respectively; (3)a main gate dielectric layer formed on the channel region; (4)a main gate layer formed on the central area of the main gate dielectric layer to expose the main gate oxide layer on two sides of the main gate layer; the main gate layer and the main gate dielectric layer underneath it forming a main gate structure; (5)a planarized insulation layer formed on the Schottky source/drain regions and the main gate structure; and (6)an island-shaped sub-gate layer formed on the insulation layer, and located over top of the main gate structure; two ends of the island-shaped sub-gate layer overlap with the Schottky source/drain regions respectively.
The forth structure of the thin film transistor with sub-gates and Schottky source/drain of the invention is comprised of: (1) a semiconductor thin film layer formed on an insulation substrate to serve as channel region of the thin film transistor; (2)two metal-containing Schottky source/drain regions formed on the insulation substrate and two sides of the channel region and form a Schottky contact with the channel region respectively;. (3)a main gate dielectric layer formed on the channel region; (4)a main gate layer formed on the central region of the gate dielectric layer; the main gate layer and the main dielectric layer underneath it forming a main gate structure; (5)an insulation mask covering a first portion of the main gate layer and the main gate dielectric layer located on the side of the first portion of the main gate layer; (6)an insulation spacer formed on the side walls of a second portion of the main gate layer and the main gate dielectric next to the second portion of the main gate layer; (7)a planarized insulation layer formed on the Schottky source/drain region, insulation spacer, insulation mask and the main gate structure; and (8)an island-shaped sub-gate layer formed on the insulation layer, which is over top of the main gate structure; wherein the two ends of the island-shaped sub-gate layer overlap with the two Schottky source/drain regions respectively.